Practical Formal Methods for Hardware Design

Formal methods for hardware design still find limited use in industry. Yet current practice has to change to cope with decreasing design times and increasing quality requirements. This research report presents results from the Esprit project FORMAT (formal methods in hardware verification) which involved the collaboration of the enterprises Siemens, Italtel, Telefonica I+D, TGI, and AHL, the research institute OFFIS, and the universities of Madrid and Passau. The work presented involves advanced specification languages for hardware design that are intuitive to the designer, like timing diagrams and state based languages, as well as their relation to VHDL and formal languages like temporal logic and a process-algebraic calculus. The results of experimental tests of the tools are also presented.

1. Formal methods vs. conventional ones.- 2. The FORMAT project.- 3. Organization of this book.- I. Overview.- Design Methodology for Complex VLSI Devices.- Specification Languages.- Verification Flow.- Synthesis Flow.- II. Industrial Experience.- Application of a Formal Verification Toolset to the Design of Integrated Circuits in an Industrial Environment.- Italtel Application of the FORMAT Design Flow.- Siemens Industrial Experience.- III. Technical Background.- The FORMAT Model Checker.- Reasoning.- VHDL Formal Modeling and Analysis.- Synthesis Techniques.- Generating VHDL Code from LOTOS Descriptions.