Metrology and Diagnostic Techniques for Nanoelectronics

Nanoelectronics is changing the way the world communicates, and is transforming our daily lives. Continuing Moore’s law and miniaturization of low-power semiconductor chips with ever-increasing functionality have been relentlessly driving R&D of new devices, materials, and process capabilities to meet performance, power, and cost requirements. This book covers up-to-date advances in research and industry practices in nanometrology, critical for continuing technology scaling and product innovation. It holistically approaches the subject matter and addresses emerging and important topics in semiconductor R&D and manufacturing. It is a complete guide for metrology and diagnostic techniques essential for process technology, electronics packaging, and product development and debugging—a unique approach compared to other books. The authors are from academia, government labs, and industry and have vast experience and expertise in the topics presented. The book is intended for all those involved in IC manufacturing and nanoelectronics and for those studying nanoelectronics process and assembly technologies or working in device testing, characterization, and diagnostic techniques.

CHARACTERIZATION AND METROLOGY FOR MOS DEVICES AND INTERCONNECTS Model-Based Scanning Electron Microscopy Critical-Dimension Metrology for 3D Nanostructures Andra´s E. Vlada´r X-Ray Metrology for Semiconductor Fabrication Daniel F. Sunday and R. Joseph Kline Advancements in Ellipsometric and Scatterometric Analysis Samuel O’Mullane, Dhairya Dixit, and Alain C. Diebold 3D-AFM Measurements for Semiconductor Structures and Devices Ndubuisi G. Orji and Ronald G. Dixson SIMS Analysis on the Transistor Scale: Probing Composition and Dopants in Nonplanar, Confined 3D Volumes Andre A. Budrevich and Wilfried Vandervorst Transistor Strain Measurement Techniques and Their Applications Markus Kuhn, Stephen Cea, Jiong Zhang, Matthew Wormington, Thomas Nuytten, Ingrid De Wolf , Jian-Min Zuo, and Jean-Luc Rouviere Scanning Spreading Resistance Microscopy (SSRM): High-Resolution 2D and 3D Carrier Mapping of Semiconductor Nanostructures Andreas Schulze, Pierre Eyben, Thomas Hantschel, and Wilfried Vandervorst Microstructure Characterization of Nanoscale Materials and Interconnects J. K. Weiss, Jai Ganesh Kameswaran, Amith Darbal, Jiong Zhang, Di Xu, and Edgar F. Rauch Characterization of the Chemistry and Mechanical Properties of Interconnect Materials and Interfaces: Impact on Interconnect Reliability Ying Zhou and Han Li Characterization of Plasma Damage for Low-k Dielectric Films Hualiang Shi, Huai Huang, Ryan S. Smith, and Paul S. Ho Defect Characterization and Metrology Tuyen K. Tran 3D Electron Tomography for Nanostructures Huolin L. Xin, Sai Bharadwaj Vishnubhotla, and Ruoqian Lin Electron Energy Loss Spectroscopy of Semiconductor Nanostructures and Oxides Wu Zhou, Maria Varela, Juan-Carlos Idrobo, Sokrates T. Pantelides, and Stephen J. Pennycook Atom Probe Tomography of Semiconductor Nanostructures Thomas F. Kelly and Karen Henry CHARACTERIZATION TECHNIQUES FOR NOVEL MATERIALS AND DEVICES BEYOND CMOS Characterization and Metrology for Graphene Materials, Structures, and Devices Luigi Colombo, Alain Diebold, Cinzia Casiraghi, Moon Kim, Robert M. Wallace, and Archana Venugopal Characterization of Magnetic Nanostructures for Spin-Torque Memory Applications with Macro- and Microscale Ferromagnetic Resonance T. J. Silva, H. T. Nembach, J. M. Shaw, Brian Doyle, Kaan Oguz, Kevin O’brien, and Mark Doczy Band Alignment Measurement by Internal Photoemission Spectroscopy Nhan V. Nguyen ELECTRICAL CHARACTERIZATION AND RELIABILITY TESTING TECHNIQUES Electrical Characterization of Nanoscale Transistors: Emphasis on Traps Associated with MOS Gate Stacks Xiao Sun and T. P. Ma Charge Pumping for Reliability Characterization and Testing of Nanoelectronic Devices Jason T. Ryan, Jason P. Campbell, Kin P. Cheung, and John S. Suehle Application of in situ Resistance and Nanocalorimetry Measurements for Nanoelectronic Thin-Film Materials Zichao Ye, Zhiyong Ma, and Leslie H. Allen CHARACTERIZATION AND METROLOGY FOR 3D STACKED DIE/PACKAGE INTERCONNECTIONS Methodology and Challenges in Characterization of 3D Package Interconnection Materials and Processes Rajen Dias and Deepak Goyal 3D Interconnect Characterization Using Raman Spectroscopy Ingrid De Wolf Advances in 3D Interconnect Characterization Techniques for Fault Isolation and Defect Imaging Wenbing Yun, Mario Pacheco, Sebastian Brand, Peter Czurratis, Matthias Petzold, Tatjana Djuric, Peter Hoffrogge, Mayue Xie, Deepak Goyal, Zhiyong Wang, Antonio Orozco, Fred C. Wellstood, and Rajen Dias CIRCUIT DIAGNOSTIC AND PROBING TECHNIQUES Optical and Electrical Nanoprobing for Circuit Diagnostics Travis Eiles, Tom Tong and Edward I. Cole, Jr. Automated Tools and Methods for Debug and Diagnosis Srikanth Venkataraman

Zhiyong Ma received his MS degree in materials engineering from Purdue University, Indiana, and a PhD in materials science and engineering from the University of Illinois, Urbana-Champaign. He worked in thin-film metallization and processing at Digital Equipment Corporation and joined Intel’s Corporate Quality Network in 1995. Currently, he is vice president of the Technology and Manufacturing Group and director of Technology Development and Manufacturing Labs at Intel, responsible for the CQN lab network in support of silicon and assembly technology development and manufacturing, product fault diagnostics, and silicon and platform benchmarking, including strategic business planning, analytical technique development, and metrology roadmaps. Dr. Ma holds 8 patents in underbump metallization, strained silicon transistors, secured fuse technology, and silicon diagnostic techniques, has published more than 25 refereed papers, and has coauthored a book chapter on silicide technology. His research interests include thin-film kinetics, analytical techniques and metrology, and product fault diagnostics. David G. Seiler received his PhD and MS in physics from Purdue University and a BS in physics from Case Western Reserve University, Ohio. He is a fellow of the American Physical Society and a fellow of the Institute of Electrical and Electronic Engineers. In 2000, he received a Distinguished Alumni Award from Purdue University's School of Science for his contributions to and achievements in semiconductors. He served as solid state physics program director in the Materials Research Division, National Science Foundation; spent a year’s sabbatical at the MIT Francis Bitter National Magnet Laboratory; and was a regents’ professor of physics at the University of North Texas. He joined the National Institute of Standards and Technology (NIST) in 1988 and served as program analyst in the program office for the director of NIST and as materials technology group leader in the Engineering Physics Division. Currently, he is chief of the division, which provides technical leadership in measurement science research, development, and standards essential to improving US economic competitiveness for advanced manufacturing. Dr. Seiler has been the chairperson and proceedings editor of 15 international conferences or workshops. He is the coeditor and coauthor of a chapter in Semiconductors and Semimetals (1992, Vol. 36) and a coauthor of a chapter in Handbook of Optics (1995, revised 2009). His current research focus is on understanding and advancing the metrology and characterization measurements needed for the future of nanoelectronics. The results of his research have been disseminated in over 200 publications and 100 talks throughout the world.