Electronic Design Automation for Integrated Circuits Handbook, Second Edition - Two Volume Set

Comprised of two volumes, Electronic Design Automation for Integrated Circuits Handbook, Second Edition addresses all major areas of EDA for integrated circuits (ICs). Chapters contributed by leading experts authoritatively discuss an array of topics ranging from system design to physical implementation. New to This Edition: Major updates appearing in the initial phases of the design flow, where the level of abstraction keeps rising to support more functionality with lower non-recurring engineering (NRE) costs Significant revisions reflected in the final phases of the design flow, where the complexity due to smaller and smaller geometries is compounded by the slow progress of shorter wavelength lithography New coverage of cutting-edge applications and approaches realized in the decade since publication of the previous edition—these are illustrated by new chapters on high-level synthesis, system-on-chip (SoC) block-based design, back-annotating system-level models, 3D circuit integration, and clock design Offering improved depth and modernity, Electronic Design Automation for Integrated Circuits Handbook, Second Edition – Two-Volume Set provides a valuable, state-of-the-art reference for EDA students, researchers, and professionals.

INTRODUCTION OverviewLuciano Lavagno, Grant E. Martin, Louis K. Scheffer, and Igor L. Markov Integrated Circuit Design Process and Electronic Design AutomationRobert Damiano, Raul Camposano, and Grant E. Martin Tools and Methodologies for System-Level DesignShuvra Bhattacharyya and Marilyn Wolf System-Level Specification and Modeling LanguagesStephen A. Edwards and Joseph T. Buck SoC Block-Based Design and IP AssemblyYaron Kashai Performance Evaluation Methods for Multiprocessor System-on-Chip DesignAhmed Jerraya and Iuliana Bacivarov System-Level Power ManagementNaehyuck Chang, Enrico Macii, Massimo Poncino, and Vivek Tiwari Processor Modeling and Design ToolsAnupam Chattopadhyay, Nikil Dutt, Rainer Leupers, and Prabhat Mishra Models and Tools for Complex Embedded Software and SystemsMarco Di Natale SYSTEM-LEVEL DESIGN Using Performance Metrics to Select Microprocessor Cores for IC DesignsSteve Leibson High-Level SynthesisFelice Balarin, Alex Kondratyev, and Yosinori Watanabe MICROARCHITECTURE DESIGN Back-Annotating System-Level ModelsMiltos D. Grammatikakis, Antonis Papagrigoriou, Polydoros Petrakis, and Marcello Coppola Microarchitectural and System-Level Power Estimation and OptimizationEnrico Macii, Renu Mehra, Massimo Poncino, and Robert P. Dick Design PlanningRalph H.J.M. Otten Design and Verification LanguagesStephen A. Edwards Digital SimulationJohn Sanguinetti Leveraging Transaction-Level Models in an SoC Design FlowLaurent Maillet-Contoz, Jérôme Cornet, Alain Clouard, Eric Paire, Antoine Perrin, and Jean-Philippe Strassen LOGIC VERIFICATION Assertion-Based VerificationHarry Foster and Erich Marschner Hardware-Assisted Verification and Software DevelopmentFrank Schirrmeister, Mike Bershteyn, and Ray Turner Formal Property VerificationLimor Fix, Ken McMillan, Norris Ip, and Leopold Haller TEST Design-for-TestBernd Koenemann and Brion Keller Automatic Test Pattern GenerationKwang-Ting (Tim) Cheng, Li-C. Wang, Huawei Li, and James Chien-Mo Li Analog and Mixed-Signal TestHaralampos-G. Stratigopoulos and Bozena Kaminska RTL TO GDSII, OR SYNTHESIS, PLACE, AND ROUTE Design FlowsDavid Chinnery, Leon Stok, David Hathaway, and Kurt Keutzer Logic SynthesisSunil P. Khatri and Narendra V. Shenoy Power Analysis and Optimization from Circuit to Register-Transfer LevelsJosé Monteiro, Rakesh Patel, and Vivek Tiwari Equivalence CheckingAndreas Kuehlmann and Fabio Somenzi Digital Layout: PlacementAndrew B. Kahng and Sherief Reda Static Timing AnalysisJordi Cortadella and Sachin S. Sapatnekar Structured Digital DesignMinsik Cho, Mihir Choudhury, Ruchir Puri, Haoxing Ren, Hua Xiang, Gi-Joon Nam, Fan Mo, and Robert K. Brayton RoutingGustavo E. Téllez, Jin Hu, and Yaoguang Wei Physical Design for 3D ICsSung-Kyu Lim Gate SizingStephan Held and Jiang Hu Clock Design and SynthesisMatthew R. Guthaus Exploring Challenges of Libraries for Electronic DesignJames Hogan, Scott T. Becker, and Neal Carney Design ClosurePeter J. Osler, John M. Cohn, and David Chinnery Tools for Chip-Package CodesignPaul D. Franzon and Madhavan Swaminathan Design DatabasesMark Bales FPGA Synthesis and Physical DesignMike Hutton, Vaughn Betz, and Jason Anderson ANALOG AND MIXED-SIGNAL DESIGN Simulation of Analog and RF Circuits and SystemsJaijeet Roychowdhury and Alan Mantooth Simulation and Modeling for Analog and Mixed-Signal Integrated CircuitsGeorges G.E. Gielen and Joel R. Phillips Layout Tools for Analog Integrated Circuits and Mixed-Signal Systems-on-Chip: A SurveyRob A. Rutenbar, John M. Cohn, Mark Po-Hung Lin, and Faik Baskaya PHYSICAL VERIFICATION Design Rule CheckingRobert Todd, Laurence Grodd, Jimmy Tomblin, Katherine Fetty, and Daniel Liddell Resolution Enhancement Techniques and Mask Data PreparationFranklin M. Schellenberg Design for Manufacturability in the Nanometer EraNicola Dragone, Carlo Guardiani, and Andrzej J. Strojwas Design and Analysis of Power Supply NetworksRajendran Panda, Sanjay Pant, David Blaauw, and Rajat Chaudhry Noise in Digital ICsIgor Keller and Vinod Kariat Layout ExtractionWilliam Kao, Chi-Yuan Lo, Mark Basel, Raminderpal Singh, Peter Spink, and Louis K. Scheffer Mixed-Signal Noise Coupling in System-on-Chip Design: Modeling, Analysis, and ValidationNishath Verghese and Makoto Nagata TECHNOLOGY CAD Process SimulationMark D. Johnson Device Modeling: From Physics to Electrical Parameter ExtractionRobert W. Dutton, Chang-Hoon Choi, and Edwin C. Kan High-Accuracy Parasitic ExtractionMattan Kamon and Ralph Iverson

Luciano Lavagno received his PhD in electrical engineering and computer sciences from the University of California, Berkeley, USA (UC Berkeley), in 1992, and from Politecnico di Torino, Italy, in 1993. He is a coauthor of two books on asynchronous circuit design, a book on hardware/software codesign of embedded systems, more than 200 scientific papers, and 12 US patents. Between 1993 and 2000, he was the architect of the POLIS project, a cooperation between UC Berkeley, Cadence Design Systems, Magneti Marelli, and Politecnico di Torino, which developed a complete hardware/software codesign environment for control-dominated embedded systems. Between 2003 and 2014, he was one of the creators and architects of the Cadence C-to-Silicon high-level synthesis system. Since 2011, he has been a full professor with Politecnico di Torino. He has been serving on the technical committees of several international conferences, workshops, and symposia. He has been the technical program chair of the Design Automation Conference, and the technical program committee and general chair of the International Conference on Hardware/Software Codesign and System Synthesis. He has been an associate editor of the Institute of Electrical and Electronics Engineers (IEEE) Transactions on Circuits and Systems and Association for Computing Machinery (ACM) Transactions on Embedded Computing. He is a senior member of the IEEE. His research interests include the synthesis of asynchronous low-power circuits, the concurrent design of mixed hardware and software embedded systems, the high-level synthesis of digital circuits, the design and optimization of hardware components and protocols for wireless sensor networks (WSNs), and design tools for WSNs. Igor L. Markov is currently on leave from the University of Michigan, Ann Arbor, USA, where he taught for many years. He joined Google in 2014 and occasionally teaches very-large-scale integration design at Stanford University, California, USA. He researches computers that make computers, including algorithms and optimization techniques for electronic design automation, secure hardware, and emerging technologies. He is an Institute of Electrical and Electronics Engineers (IEEE) fellow and an Association for Computing Machinery (ACM) distinguished scientist. He has coauthored five books, and has four U.S. patents and more than 200 refereed publications, some of which were honored by best-paper awards. Professor Markov is a recipient of the Design Automation Conference Fellowship, ACM Special Interest Group on Design Automation Outstanding New Faculty Award, National Science Foundation Faculty Early Career Development Program Award, IBM Partnership Award, Microsoft A. Richard Newton Breakthrough Research Award, and IEEE Council on Electronic Design Automation Early Career Award. During the 2011 redesign of the ACM Computing Classification System, Professor Markov led the effort on the hardware tree. Twelve doctoral dissertations were defended under his supervision; three of which received outstanding dissertation awards. Grant E. Martin is a distinguished engineer at Cadence Design Systems, Inc., San Jose, California, USA. Before that, Grant worked for Burroughs in Scotland for 6 years; Nortel/Bell-Northern Research in Canada for 10 years; Cadence Design Systems for 9 years, eventually becoming a fellow in their labs; and Tensilica for 9 years. He rejoined Cadence in 2013 when it acquired Tensilica, and has been there since, working in the Tensilica part of the Cadence Intellectual Property Group. He received his bachelor’s and master’s degrees in mathematics (combinatorics and optimization) from the University of Waterloo, Ontario, Canada, in 1977 and 1978. Grant has coauthored and coedited several books, including the first-ever book on system-on-chip (SoC) design published in Russian. He has also presented many papers, talks, and tutorials, and participated in panels at a number of major conferences. He cochaired the VSI Alliance Embedded Systems Study Group in the summer of 2001, and was cochair of the Design Automation Conference Technical Program Committee for Methods for 2005 and 2006. He is also a coeditor of the Springer Embedded Systems series. His particular areas of interest include system-level design, intellectual property-based design of SoC, platform-based design, digital signal processing, baseband and image processing, and embedded software. He is a senior member of the Institute of Electrical and Electronics Engineers. Louis K. Scheffer received his BS and MS from the California Institute of Technology, Pasadena, USA, in 1974 and 1975, and his PhD from Stanford University, California, USA, in 1984. He worked at Hewlett Packard from 1975 to 1981 as a chip designer and computer-aided design tool developer. In 1981, he joined Valid Logic Systems, where he did hardware design, developed a schematic editor, and built an integrated circuit layout, routing, and verification system. In 199