Low Power Networks-on-Chip

TRAMA

In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities. This book offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures.

SOMMARIO

Network-on-Chip Power Estimation.- Timing.- synchronous/asynchronous communication.- Network-on-Chip link design.- Topology exploration.- Network-on-Chip support for CMP/MPSoCs.- Network design for 3D stacked logic and memory.- Beyond the wired Network-on-Chip.

ALTRE INFORMAZIONI

• Condizione: Nuovo
• ISBN: 9781441969101
• Dimensioni: 235 x 155 mm
• Formato: Copertina rigida
• Illustration Notes: XIX, 287 p.
• Pagine Arabe: 287
• Pagine Romane: xix