Emerging Technologies and Circuits

TRAMA

With the semiconductor market growth, new Integrated Circuit designs are pushing the limit of the technology and in some cases, require specific fine-tuning of certain process modules in manufacturing. Thus the communities of design and technology are increasingly intertwined. The issues that require close interactions and collaboration for trade-off and optimization across the design/device/process fields are addressed in Emerging Technologies and Circuits. It contains a set of outstanding papers, keynote and tutorials presented during 3 days at the International Conference On Integrated Circuit Design and Technology (ICICDT) held in June 2008 in Minatec, Grenoble. The selected papers are spread over 5 chapters covering various aspects of emerging technologies and devices, advanced circuit design, reliability, variability issues and solutions, advanced memories and analog and mixed signals. All these papers are focusing on design and technology interactions and comply with the scope of the conference.

SOMMARIO

Synergy Between Design and Technology: A Key Factor in the Evolving Microelectronic Landscape.- EMERGING TECHNOLOGY AND DEVICES.- New State Variable Opportunities Beyond CMOS: A System Perspective.- A Simple Compact Model to Analyze the Impact of Ballistic and Quasi-Ballistic Transport on Ring Oscillator Performance.- ADVANCED DEVICES AND CIRUITS.- Low-Voltage Scaled 6T FinFET SRAM Cells.- Independent-Double-Gate FINFET SRAM Cell for Drastic Leakage Current Reduction.- Metal Gate Effects on a 32 nm Metal Gate Resistor.- RELIABILITY AND SEU.- Threshold Voltage Shift Instability Induced by Plasma Charging Damage in MOSFETS with High-K Dielectric.- Analysis of SI Substrate Damage Induced by Inductively Coupled Plasma Reactor with Various Superposed Bias Frequencies.- POWER, TIMING AND VARIABILITY.- CMOS SOI Technology for WPAN: Application to 60 GHZ LNA.- SRAM Memory Cell Leakage Reduction Design Techniques in 65 nm Low Power PD-SOI CMOS.- Resilient Circuits for Dynamic Variation Tolerance.- Process Variability-Induced Timing Failures – A Challenge in Nanometer CMOS Low-Power Design.- How Does Inverse Temperature Dependence Affect Timing Sign-Off.- CMOS Logic Gates Leakage Modeling Under Statistical Process Variations.- On-Chip Circuit Technique for Measuring Jitter and Skew with Picosecond Resolution.- ANALOG AND MIXED SIGNAL.- DC–DC Converter Technologies for On-Chip Distributed Power Supply Systems – 3D Stacking and Hybrid Operation.- Sampled Analog Signal Processing: From Software-Defined to Software Radio.

ALTRE INFORMAZIONI

• Condizione: Nuovo
• ISBN: 9789400733534
• Collana: Lecture Notes in Electrical Engineering
• Dimensioni: 235 x 155 mm
• Formato: Brossura
• Illustration Notes: X, 266 p.
• Pagine Arabe: 266
• Pagine Romane: x