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Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs
noia brandon; chakrabarty krishnendu
108,98 €
103,53 €
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TRAMA
This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.SOMMARIO
Introduction.- Wafer Stacking and 3D Memory Test.- Built-in Self-Test for TSVs.- Pre-Bond TSV Test Through TSV Probing.- Pre-Bond TSV Test Through TSV Probing.- Overcoming the Timing Overhead of Test Architectures on Inter-Die Critical Paths.- Post-Bond Test Wrappers and Emerging Test Standards.- Test-Architecture Optimization and Test Scheduling.- Conclusions.AUTORE
Krishnendu Chakrabarty is a Professor of Electrical and Computer Engineering at Duke University. He received his PhD from University of Michigan. He is a Fellow of IEEE and a Distinguished Engineer of ACM.ALTRE INFORMAZIONI
- Condizione: Nuovo
- ISBN: 9783319023779
- Dimensioni: 235 x 155 mm Ø 5685 gr
- Formato: Copertina rigida
- Illustration Notes: XVIII, 245 p. 133 illus., 115 illus. in color.
- Pagine Arabe: 245
- Pagine Romane: xviii